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CEA-Leti and ST-Ericsson to Present Paper on Breakthrough 3DIC with Wide I/O Interface
Collaboration between CEA-Leti, ST-Ericsson and Cadence on 3DIC Stack Design
WHO
Pascal Vivet, researcher for CEA-Leti, a French research-and-technology organization and Vincent Guerin, senior digital design engineer, ST-Ericsson
WHAT
CEA-Leti and ST-Ericsson will present a paper entitled, “A Three-Layer 3DIC Stack Including Wide I/O and 3D Network-on-Chip (NoC) – Practical Design Perspective.”
The paper details the creation of a prototype of the world’s first 3DIC with a three-die stack, an important milestone in validating and testing essential 3D technologies including Wide I/O memory and inter-chip communications protocols.
The design is the result of a close collaboration among CEA-Leti, ST-Ericsson—a world leader in wireless platforms and semiconductors, and Cadence Design Systems, Inc. (NASDAQ: CDNS)—a leader in global electronic design innovation.
WHEN
December 13, 2011, 3:15 p.m.
WHERE
3D Architectures for Semiconductor Integration and Packaging Conference
Hyatt Regency San Francisco Airport Hotel
Burlingame, CA
BACKGROUND
Leti has designed with partners ST-Ericsson and Cadence a major advance in 3D IC stacking. The design integrates three stacked dies, integrating a Wide I/O DRAM memory stacked on top of two identical SOC logic die that incorporate multiple processor cores on each die. TSVs (through-silicon vias) connect these three die together and in order to minimize the impact of the TSVs on signal integrity, the 3D stack employs an asynchronous Network on a Chip (NoC) for both die-to-die and intra-die communications. The 3D-friendly NoC employs asynchronous serial links and achieves 550M transfers/sec throughput in the 2D (intra-die) direction, and 200M transfers/sec in the 3D (inter-die) direction. Together with the high throughput and low power Wide I/O memory interface, this advanced three-die 3D prototype represents a first proof of concept, clearly demonstrating how these technologies can be employed to efficiently stack memory and logic for future 3D multi-processor architectures.
For its part of the joint project, ST-Ericsson developed WIOMING, the first application processor SOC integrated with a Wide I/O memory interface. Combined with Wide I/O technology, TSV and fine-pitch bumping technologies permit massive, high-bandwidth interconnect between the DRAM and SOC with very low capacitive and inductive loading. This approach also reduces interface power dissipation in the DRAM and logic die. The ST-Ericsson WIOMING SOC provides 12.8GBytes/s of memory bandwidth – a 50 percent increase over the latest available dual channel LPDDR2 solutions at 533MHz at 20 percent less power. In addition, increasing the DRAM interface clock frequency to 266MHz and switching to DDR (dual data rate) mode will allow ST-Ericsson to create designs that deliver more than 34GBytes/s in future products, enabling unprecedented graphics and CPU performance in product such as smartphones and tablets.
Cadence has worked closely with ST-Ericsson and Leti to deliver the design tools and methodologies necessary for enabling this breakthrough three-layer 3D IC. The company developed an automated and integrated 3D/TSV design solution employing the industry-leading physical implementation and analysis features in its Encounter Digital Implementation (EDI) System, Virtuoso Analog Design Environment, and QRC parasitic extraction tool. The project design team then used these tools to address complex timing, signal integrity, and thermal challenges in the 3D design. As a result of this collaboration on tools and methodology, the design teams have successfully taped out multiple 3D/TSV designs. In addition, the teams incorporated the Cadence Wide I/O memory controller design IP into the design of the WIOMING SoC, ensuring exceptionally high bandwidth memory.
About CEA-Leti
Leti is an institute of CEA, a French research-and-technology organization with activities in energy, IT, healthcare, defence and security. Leti is focused on creating value and innovation through technology transfer to its industrial partners. It specializes in nanotechnologies and their applications, from wireless devices and systems, to biology, healthcare and photonics. NEMS and MEMS are at the core of its activities. An anchor of the MINATEC campus, CEA-Leti operates 8,000-m² of state-of-the-art clean room space on 200mm and 300mm wafer platforms. It employs 1,400 scientists and engineers and hosts more than 190 Ph.D. students and 200 assignees from partner companies. CEA-Leti owns more than 1,700 patent families. For more information, visit www.leti.fr.
About ST-Ericsson
ST-Ericsson is a world leader in developing and delivering a complete portfolio of innovative mobile platforms and cutting-edge wireless semiconductor solutions across the broad spectrum of mobile technologies. The company is a leading supplier to the top handset manufacturers and generated sales of $2.3 billion in 2010. ST-Ericsson was established as a 50/50 joint venture by STMicroelectronics (NYSE:STM) and Ericsson (NASDAQ:ERIC) in February 2009, with headquarters in Geneva, Switzerland.
Media contacts:
CEA-Leti
Thierry Bosc
Email: thierry.bosc@cea.fr
ST-Ericsson Media Relations
Pamela McCracken
Email: media.relations@stericsson.com