Digital electronics are pervasive across the globe today, enriching people’s lives, and making communication and sharing easier than ever. To build better digital devices and enhance the user experience, the size of the transistors composing the ICs must be reduced while increasing performance and reducing power consumption.
But, as transistors shrink new challenges arise and innovative solutions must be found to continue to deliver the full benefits of the technology advance.
Some unwanted leakage current flows even when the transistor is switched off. This leakage current has been increasing with every new generation of transistor and represents a growing proportion of power consumption
In order to minimize this leakage while continuing to deliver high performance, bulk silicon transistors have become ever more complex adding additional levels of manufacturing complexity at an ever increasing rate.
Fully Depleted Silicon On Insulator, or FD-SOI, is an approach that delivers the benefits of reduced silicon geometries while enabling a simplification of the manufacturing process.
Unlike some other technologies, FD-SOI does not change the fundamental geometry of the transistor. In FD-SOI, the innovation lies in adding a thin layer of insulator, called the buried oxide, positioned just below the channel.
This buried oxide layer eliminates the need to add dopants to the channel, thus making it “fully depleted”.
Another key innovative step versus previous techniques is that the silicon on oxide layer is very thin. Together with the thin body channel layer this technology is called “ultra-thin body and buried oxide” or UTBB.
In order to improve the transistor performance, a voltage can be applied to the silicon substrate. This method, called “body biasing”, facilitates the flow of electrons, resulting in faster switching of the transistor. Thanks to the ultra-thin insulator layer in FD-SOI, the biasing creates a buried gate below the channel making the FD-SOI act like a vertical double gate transistor.
Unlike bulk technology, where the biasing is very limited, due to parasitic current leakage, the buried gate on the FD-SOI transistor prevents any leakage in the substrate. This allows a much higher voltage on the body, leading to a significant boost in performance.
The Buried oxide layer efficiently confines the electrons when flowing from the source to the drain, drastically reducing the leakage currents from the channel to the substrate. Since in 28nm and beyond, these leakage represents a significant proportion of the power consumption, FD-SOI brings a significant improvement in power saving. This also makes the FD-SOI chip cooler.
Different voltages can be applied independently to the top and the buried gates of the FD-SOI transistor, which effectively change its characteristics. By choosing optimal combinations of the voltages, the transistor characteristics can be transformed from those of a very high performance transistor to those of a very low power transistor. A processing core built up of such transistors can operate as if it were in fact two cores – one optimized for high performance and the other for low power.
FD-SOI is a planar technology that re-uses ninety percent of the process steps used in 28nm bulk. The overall manufacturing process in FD-SOI is 12% less complex leading to lower cycle time and reduced manufacturing costs. The manufacturing tools for FD-SOI are much simpler than those required for recent advanced processes such as complex FinFet 3D technology.
Moreover, when designing a chip in FD-SOI most of the IP blocks can be directly re-used from a bulk design, making the porting of an existing design to FD-SOI extremely simple and fast.
FD-SOI is available today in 28nm and the roadmap is already defined up the 10nm node. The 14nm node is already in development.
FD-SOI: A process booster for ST-Ericsson’s next generation NovaThor", b